As is known, highly complex integrated circuits, such as microprocessors fabricated on a single chip, comprise a plurality of input/output devices for interfacing the circuits with external user's facilities.
Input/output devices can be programmed independently to receive data being input to the circuit or deliver output data from the circuit.
Referring to FIG. 1, an integrated circuit 1 as above comprises at least one central processing unit CPU and at least a plurality of peripheral units and internal memories PF, which in FIG. 1 have been unitized for simplicity into a single bloc designated CPU/PF.
In general, the central processing unit CPU and plurality of peripheral units and internal memories PF are implemented as plural modules, each conceived to perform a specific function.
These modules are interfaced with one another by means of a system channel, or bus, designated BUS1 in FIG. 1.
The channel BUS1 conveys system signals, which may be data, addresses, or control signals transmitted and received by the individual modules under control from the CPU.
Each module includes an interface circuit, not shown in FIG. 1 because conventional, which is arranged to interface the module with the channel BUS1, and therefore, with the other modules in the system.
The integrated circuit 1 also comprises a plurality of input/output devices I/O.
Each input/output device I/O comprises a pad P for interfacing the circuit 1 with the outside world, and a protection circuit for the pad.
This protection circuit is designated ESD in FIG. 1, and is not shown in detail because it is conventional.
Each input/output device I/O further comprises control logic circuitry LC connected to the system channel BUS1 and also omitted from FIG. 1 because conventional.
The control circuitry LC includes data registers for storing data from the channel BUS1 to be written to the pads, and data to be read from the pads and delivered on the channel BUS1.
The control circuitry also includes control registers for storing the control signals which allow the input buffer and output buffer to be driven such that the device I/O can be programmed for different configurations (bi-directional mode, input mode, o output mode).
It should be considered here that, by reason of their specific functions, the input/output devices I/O are usually designed as bits; each input/output device generally comprising 8 bits.
In the circuit 1, each bit is placed near a pad.
This conventional architecture for input/output devices I/O has significant disadvantages in terms of the area occupied by the integrated circuit and performance of the integrated circuit.
In fact, the channel BUS1, which is to serve the CPU, as well as the peripheral units and internal memories PF, and the input/output devices I/O, should have a so-called "loop" path in order for each bit to be supplied of the individual input/output devices.
This clearly requires extra area specially for the channel BUS1, in addition to the area required for supplying the CPU, peripherals and internal memories.
Furthermore, the looped path of the channel BUS1 affects the so-called "electric capacitance" of the channel, which is made higher.
A high electric capacitance involves longer propagation times for the signals along the channel, thereby limiting the "frequency" performance of the integrated circuit.